純記錄
module Test(
output
[7:0] seg,
output
[3:0] dig,
output
reg led,
input
clock
);
reg
[14:0] number; // number to display
reg
[25:0] clock_divider;
wire
[3:0] D3;
wire
[3:0] D2;
wire
[3:0] D1;
wire
[3:0] D0;
assign
seg7_clk = clock_divider[14];
BIN2BCD
bin2bcd(number, D3, D2, D1, D0);
Seg7 seg7(seg, dig, seg7_clk, D3, D2, D1, D0);
//
initial
initial
begin
clock_divider
= 0;
number
= 0;
end
//
number counts
always
@ (posedge clock )
begin
clock_divider
= clock_divider + 1'b1;
if(clock_divider==25'd25000000)
begin
clock_divider
= 0;
number
= number+ 1;
if
(number==14'd10000)
begin
number
= 0;
end
end
end
endmodule
|
/*
Bin2BCD:
Convert binary to 4 BCDs
*/
module BIN2BCD(
input
[14:0] binary,
output
reg [3:0] BCD3,
output
reg [3:0] BCD2,
output
reg [3:0] BCD1,
output
reg [3:0] BCD0
);
integer
i;
always@(binary)
begin
BCD3
= 4'd0;
BCD2
= 4'd0;
BCD1
= 4'd0;
BCD0
= 4'd0;
for
(i=14; i>=0; i=i-1)
begin
if
(BCD3>=5)
BCD3
= BCD3 + 3;
if
(BCD2>=5)
BCD2
= BCD2 + 3;
if
(BCD1>=5)
BCD1
= BCD1 + 3;
if
(BCD0>=5)
BCD0
= BCD0 + 3;
BCD3
= BCD3 << 1;
BCD3[0]
= BCD2[3];
BCD2
= BCD2 << 1;
BCD2[0]
= BCD1[3];
BCD1
= BCD1 << 1;
BCD1[0]
= BCD0[3];
BCD0
= BCD0 << 1;
BCD0[0]
= binary[i];
end
end
endmodule
|
/*
4-digit
7-Segment LED display
*/
module Seg7(
output
reg [7:0] seg,
output
reg [3:0] dig,
input clk,
input
[3:0] D3,
input
[3:0] D2,
input
[3:0] D1,
input
[3:0] D0
);
reg
[3:0] disp_dat;
initial
begin
dig=
4'b1110;
end
//
scan digits
always
@ (posedge clk)
begin
dig
= {dig[2:0],dig[3]};
case
(dig)
4'b1110
: disp_dat = D0;
4'b1101
: disp_dat = D1;
4'b1011
: disp_dat = D2;
4'b0111
: disp_dat = D3;
default
: disp_dat = 4'hf;
endcase
end
//
scan display
always
@ (disp_dat)
begin
case
(disp_dat)
4'h0
: seg = 8'hc0; //"0"
4'h1
: seg = 8'hf9; //"1"
4'h2
: seg = 8'ha4; //"2"
4'h3
: seg = 8'hb0; //"3"
4'h4
: seg = 8'h99; //"4"
4'h5
: seg = 8'h92; //"5"
4'h6
: seg = 8'h82; //"6"
4'h7
: seg = 8'hf8; //"7"
4'h8
: seg = 8'h80; //"8"
4'h9
: seg = 8'h90; //"9"
4'ha
: seg = 8'h88; //"a"
4'hb
: seg = 8'h83; //"b"
4'hc
: seg = 8'hc6; //"c"
4'hd
: seg = 8'ha1; //"d"
4'he
: seg = 8'h86; //"e"
4'hf
: seg = 8'h8e; //"f"
endcase
end
//always @ (disp_dat)
endmodule
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